This report provides a comprehensive analysis of the global and China SerDes IP and related interconnect chip industry, covering basic industry definitions, technical architecture, product categories, industrial chain structure, market size, competitive landscape, downstream applications, and future development trends.
Driven by rapid growth in AI computing demands, data center infrastructure continues to evolve, and the bandwidth constraints between computing chips and high-speed interconnects become more apparent. SerDes IP and related high-speed interconnect chips are essential underlying technologies that support high-speed interconnection of AI servers, switches, AEC copper cables, and optical modules. As 112G and above high-speed SerDes technologies mature, the industry is moving towards higher speeds such as 100G/112G, leading to comprehensive upgrades in high-speed communication links.
SerDes IP, as a core high-speed serial/deserialization module at the chip level, is widely integrated into ASICs, AI acceleration chips, switch chips, and optical communication DSPs. It serves as the fundamental component for building the “computing interconnect network” in data centers. Along with Retimers, AEC high-speed copper cable control chips, and optical oDSPs, it forms the high-speed interconnect chip system, meeting all scenarios from internal chip interconnection to rack-level and data center-level communication links.
In terms of competition, the global market has been dominated by international manufacturers such as Broadcom, Marvell, Cadence, and Synopsys. Chinese manufacturers are rapidly catching up in areas like high-speed SerDes IP, Retimers, and optical oDSPs, gradually achieving domestic substitution in low-to-mid speed and some high-speed applications.
In the future, as AI computing clusters grow larger, 800G/1.6T optical interconnection becomes more common, and new architectures such as co-packaged optics are implemented, SerDes IP and related interconnect chips will continue to evolve toward higher speeds, lower power consumption, and greater integration. They will become one of the key drivers for upgrading AI data center infrastructure, supporting high-density interconnection and efficient transmission in global computing networks over the long term.
This report analyzes the global and China SerDes IP and interconnect chip industry, covering definitions, technology architecture, market structure, competitive landscape, and key application scenarios.
Due to the rapid growth in AI computing demands, data center bandwidth requirements are increasing significantly, and SerDes IP and related high-speed interconnect chips are becoming crucial enabling technologies for AI servers, switches, AEC copper links, and optical modules. The industry is shifting toward 100G/112G+ SerDes standards, accelerating improvements in high-speed connectivity.
As a core high-speed serializer/deserializer IP, SerDes is widely used in ASICs, AI accelerators, switches, and optical DSPs. Together with Retimers, AEC controllers, and optical oDSPs, it forms the backbone of data center interconnect infrastructure, enabling end-to-end high-speed communication.
The global market is led by Broadcom, Marvell, Cadence, and Synopsys, while Chinese companies are making progress in SerDes IP, Retimers, and optical oDSPs, achieving gradual breakthroughs in certain areas.
Looking ahead, AI cluster expansion, 800G/1.6T adoption, and CPO-based architectures will continue to drive SerDes IP toward higher speed, lower power consumption, and greater integration, making it a fundamental enabler of AI data center interconnect evolution.
If you have further research needs regarding the global and China SerDes IP and related interconnect chip market, please contact us:
Ms. Jenny Cheng, Frost & Sullivan
E-mail: jenny.cheng@frostchina.com
