National Day Special 4: From Full-Chain R&D to System Coordination: Interpretation of the Development Trends of China's Semiconductor Industry during the '15th Five-Year Plan' Period

In September 2026, the Ministry of Industry and Information Technology and the National Development and Reform Commission jointly issued the "15th Five-Year Plan for the Development of Electronic Information Manufacturing" (hereinafter referred to as the "Plan"). The Plan proposes to promote full-chain research on integrated circuits and makes arrangements in areas such as advanced computing, artificial intelligence hardware, and industry electronics. The "Suggestions of the Central Committee of the Communist Party of China on Formulating the 15th Five-Year Plan for National Economic and Social Development" and the "Outline of the 15th Five-Year Plan for National Economic and Social Development of the People's Republic of China" (hereinafter referred to as the "Outline") also make arrangements for key core technologies in key areas such as integrated circuits.

From central deployment to industry planning, policies related to the semiconductor industry have covered multiple aspects including key technology development, industrial chain collaboration, and system applications: critical areas such as design tools and IP, manufacturing, packaging and testing, and equipment materials have been included in the deployment. High-performance chips also need to form collaboration with storage, interconnection, complete systems, and software. In the next five years, the key to industrial development will be promoting technological breakthroughs in weak links to achieve stable mass production, ensuring chip performance is fully utilized in real systems, and continuously verifying and improving through end-use applications.

The Outline proposes to strengthen research on key core technologies in strategically important areas and weak links of the industrial chain and supply chain. The Plan further proposes to develop high-end chip products such as high-performance processors and high-density memory, improve the manufacturing level of integrated circuits, promote the development and application of advanced packaging and testing technologies, and continuously enhance the supply capacity of key equipment, materials, and components. It also accelerates the development of electronic design automation tools (EDA) and intellectual property cores (IP cores).

Each link of the semiconductor industry is not developed independently. In the design stage, EDA/IP, PDK, and process rules determine whether the chip can be physically realized and successfully tested; in the manufacturing stage, equipment, materials, and process control jointly affect the process window, yield, and stable operation of the production line; packaging, testing, and customer verification are related to whether the product can meet expected performance and reliability requirements and achieve stable delivery. If a breakthrough in a single link cannot be adapted to the preceding and following links, it is difficult to transform it into replicable mass production capabilities.

Therefore, full-chain research needs to be implemented in specific products and processes. Chip design companies need to complete process adaptation based on the PDK, design rules, and IP resources of the wafer factory, and key products also need to carry out design-process coordination optimization; equipment and material companies need to conduct customer production line verification around the target process window, continuously verifying the stability of key parameters, defect levels, and batch consistency. Only when key parameters and verification results can be stably reproduced, can the research and development achievements have the basis for stable mass production and continuous supply.

The Plan also proposes to "refine mature processes and improve advanced process capabilities," reflecting the synchronized deployment of different process routes and application requirements. High-performance processors rely more on advanced processes, advanced packaging, and system integration; high-density memory has higher requirements for process, three-dimensional structure, and packaging integration capabilities; analog, power, and control chips have different requirements for accuracy, voltage resistance and loss, real-time performance, and long-term reliability. The competition in mature processes is more reflected in special process platforms, yield, cost, and customer certification, while advanced processes rely more on the coordinated progress of equipment materials, process integration, and design ecosystem.

Source: Frost & Sullivan analysis

Focusing on building an advanced computing ecosystem, the Plan proposes to accelerate research and development on advanced computing products and technical innovations such as computing architecture, data storage, high-speed interconnection, soft-hard coordination, and compute-electricity coordination. In terms of strengthening the foundation of artificial intelligence hardware, it also proposes to strengthen the coordination between artificial intelligence chips and complete system products and enhance the compatibility between artificial intelligence chips and large models, databases, etc. For AI/HPC, the peak computing power of chips is only part of the system performance; storage, interconnection, power supply, heat dissipation, and software stack will all affect the final system throughput and computing efficiency.

Large model training requires continuous exchange of parameters and intermediate data among multiple chips and nodes. Insufficient HBM bandwidth, limited interconnection between chips, or cluster communication limitations will reduce the utilization rate of computing units. The inference side is more vulnerable to constraints such as latency, concurrency, video memory or memory capacity, and data transfer efficiency. Long context and high concurrency will further increase storage pressure. Therefore, simply increasing the number of computing chips does not necessarily lead to a linear increase in system throughput. High-bandwidth memory, high-speed interconnection, power supply and heat dissipation, as well as compilers, communication libraries, and scheduling software, will directly affect system throughput, energy efficiency, and resource utilization.

After domestic AI chips enter customers' systems, adaptation work still needs to be continuously promoted. Whether the mainstream framework adaptation and operator coverage are complete, whether the compiler and drivers are stable, whether compatibility can be maintained after the update of large models, whether cluster scheduling and fault recovery are mature, will all affect customers' migration costs and equipment utilization rates. Chip companies need to continuously improve the software stack around actual workloads and jointly carry out long-term operation verification with complete system manufacturers and model developers.

Therefore, during the "15th Five-Year Plan" period, the competition for high-performance chips will focus more on effective throughput, storage and interconnection efficiency, system energy efficiency, software compatibility, and long-term operation stability, rather than just the theoretical peak of a single chip. Products that can shorten model migration and system optimization cycles, improve cluster utilization rate, and control operating costs are more conducive to large-scale deployment and continuous adoption.

Source: Frost & Sullivan analysis

As AI/HPC requirements for bandwidth and energy efficiency increase, the coordination between advanced packaging and chip architecture design is strengthening. The Plan clearly proposes to promote the development and application of advanced packaging and testing technologies and advance technological breakthroughs and applications such as three-dimensional integration. For the combination of computing chips and high-bandwidth storage such as HBM, issues such as interconnection distance, bandwidth density, power supply, and heat dissipation need to be considered comprehensively in the system design stage.

Chiplets and heterogeneous integration can combine chips with different functions and processes. 2.5D packaging achieves high-density interconnection through structures such as intermediate layers, and 3D integration further improves integration density through vertical stacking. These technologies provide a path for the coordination of computing chips and high-bandwidth storage, helping to improve bandwidth, latency, and energy efficiency. Specific solutions still need to balance chip area, interconnection requirements, thermal design, and cost, and be coordinated with manufacturing process optimization.

Multi-chip integration also increases the complexity of testing and yield control. In addition to die testing, it is necessary to verify the integrity of interconnection, power supply integrity, thermal performance, and reliability after packaging; for high-value multi-chip products, any die or interconnection failure may cause the entire package to fail, thereby amplifying the impact of individual defects on final yield and cost. Therefore, testing needs to be earlier in the design and manufacturing process. At the same time, higher power density also requires higher coordination design for substrate, bonding, thermal interface materials, and heat dissipation structures. The final yield of advanced packaging depends on the joint control of multiple links such as die, interconnection, packaging process, and testing.

In the next five years, advanced packaging will further move from single-process development to chip-packaging-system coordinated design. Chiplets and 2.5D/3D integration have increased the requirements for signal and power integrity, thermal management, interconnection between chips, and multi-chip testing. These issues need to be solved simultaneously in the stage of determining architecture and packaging solutions. Whether design companies, wafer factories, packaging and testing companies, as well as material, equipment, and EDA manufacturers can complete coordinated verification in the early stage of development will directly affect the yield, reliability, and large-scale application of advanced packaging solutions.

Source: Frost & Sullivan analysis

For semiconductor manufacturing, process miniaturization, three-dimensional structure, and advanced packaging will simultaneously increase the requirements for equipment accuracy, material consistency, measurement and testing, and process control. In terms of enhancing the supply capacity of electronic special equipment and measuring instruments, the Plan proposes to implement a plan to tackle key electronic special equipment problems and focus on developing production equipment in directions such as large-sized carrier boards, three-dimensional integration, heterogeneous integration, and miniaturization. At the same time, the Outline proposes to improve the support conditions for industrial technology services by establishing a number of industry common technology platforms, pilot verification platforms, and integrated high-efficiency quality infrastructure based on industrial clusters. For the semiconductor industry, such platforms can provide corresponding verification conditions for equipment, materials, and processes to transition from research and development to production.

Whether equipment can truly enter customers' production lines depends not on whether a single acceptance meets the standards, but on whether it can stably meet the established process window requirements in long-term operation. Equipment such as etching, deposition, and cleaning need to maintain stable key parameters and defect levels in multiple batches and long-term operation, and have good matching with the preceding and following processes; materials need to verify purity, batch consistency, defect levels, and process compatibility simultaneously. Device parameter drift, unplanned downtime, shortened maintenance cycle, or material fluctuations will ultimately be reflected in yield, operating rate, and production stability.

As the complexity of advanced logic, advanced storage, and three-dimensional packaging structures increases, measurement and testing play an even greater role in process control. Data such as critical dimensions, film thickness, stack error, and defect distribution need to be fed back to process parameter adjustment at a higher frequency to identify process drift and control the range of fluctuations. Therefore, device manufacturers not only need to meet the performance indicators of a single machine, but also need to have the ability to apply processes, data analysis, and on-site service capabilities, and jointly complete process segment verification with customers.

Therefore, the evolution of domestic equipment capabilities can be summarized as three stages: "single-point breakthrough - process segment coordination - mass production verification": In the first stage, the focus is on solving whether core equipment can complete research and development, delivery, and stable achievement of the target process; in the second stage, the focus is on verifying the parameter matching between equipment and the preceding and following processes and its impact on yield; in the third stage, it further tests cross-batch stability, defect control, spare parts maintenance, and long-term service capabilities. Pilot platforms can undertake some common verification, but to truly enter mass production, it still requires continuous accumulation of operation and yield data in customers' production lines.

Source: Frost & Sullivan analysis

In terms of strengthening the foundation of artificial intelligence hardware, the Plan proposes to strengthen the coordination between artificial intelligence chips and complete system products, accelerate the development of cloud training equipment, and develop edge inference equipment and chips for areas such as embodied intelligence and autonomous driving. At the same time, in tasks related to consumer electronics, industry electronics, and energy electronics, the Plan also proposes to develop products such as low-power processors, automotive-grade components, and advanced power semiconductors. Different applications correspond to different chip combinations, process choices, and verification priorities.

Cloud training and inference mainly increase the demand for AI processors, HBM, high-speed interconnection, power supply, and heat dissipation; edge intelligence is constrained by power budget, memory capacity, and heat dissipation space, emphasizing low latency, energy efficiency, and software-hardware compatibility. Mobile phones and wearable devices need to complete local inference under limited power consumption, and robots and vehicle terminals also need to process multiple sensor inputs in real time. Therefore, edge chips are not simply smaller versions of cloud solutions, but require re-design around requirements such as power consumption, latency, storage, and interfaces.

The technical requirements for automotive, industrial, and energy electronics are different. In addition to performance, automotive chips also need to meet wide-temperature, long-term reliability, and long-term supply requirements. Key control products also involve functional safety; industrial control places more emphasis on real-time performance, long-term reliability, and environmental adaptability; energy electronics pay more attention to voltage resistance, switching loss, thermal reliability, and system efficiency, putting different requirements on power devices, drive chips, and power management chips. Correspondingly, for specific products, automotive MCUs, analog and sensing chips, industrial MCUs/FPGA, IGBTs, and SiC/GaN devices all have different verification and introduction paths.

Application scenarios not only determine product requirements but also directly affect chip specification definition. Terminal and system companies need to clarify requirements such as computing power, power consumption, interface, temperature rating, lifespan, and reliability in the early stage of research and development. Chip design companies then complete architecture and product definition based on this, and conduct verification simultaneously with manufacturing, packaging, and testing. Especially in fields such as automotive, industrial, and robotics with long verification cycles, clarifying these requirements in the early stage of research and development can reduce repeated design due to process, packaging, or reliability mismatches in later stages.

The Outline proposes to support technology-driven backbone enterprises to lead the formation of innovation alliances to carry out key common technology research and development, as well as pilot testing and demonstration applications of scientific and technological achievements. In the semiconductor industry, such mechanisms can enable sample verification, system testing, and application feedback to enter the industrialization process earlier, allowing chips to continuously accumulate performance, reliability, and delivery data in real terminals and systems, providing a basis for subsequent large-scale applications.

Combining the relevant arrangements of the Outline and the Plan, the semiconductor industry policy during the "15th Five-Year Plan" period covers key technologies in the full chain of integrated circuits, as well as advanced computing, artificial intelligence hardware, electronic special equipment, and end products and industry applications. Against this background, whether design rules, manufacturing processes, and product requirements can achieve effective matching among design, manufacturing, packaging and testing, equipment, materials, and EDA/IP will directly affect whether technical achievements can enter stable mass production. The development of AI computing power has expanded competition from a single chip to computing, storage, interconnection, packaging, power supply and heat dissipation, and software systems; automotive, industrial, robot, and energy electronics require considering reliability, real-time performance, and long-term supply in the chip definition stage. In the next five years, the improvement of China's semiconductor industry capabilities will ultimately be reflected in whether technical breakthroughs can be transformed into stable mass production and continuous supply capabilities, and maintaining stable performance and reliability in real applications.